1. Field of the Invention
The invention relates to a semiconductor memory device and a method of fabricating the same, and more particularly to an improvement for SRAM cell in which MOSFET formed on a semiconductor substrate is electrically connected to a thin film transistor formed above the MOSFET with an insulating film sandwiched therebetween.
2. Description of the Related Art
As one of conventional SRAM memory cells is known a semiconductor memory cell including a pair of transfer transistors and a pair of driver transistors both of which are formed on a semiconductor substrate, and a pair of thin film load transistors (hereinafter, a thin film transistor is referred to simply as "TFT") which are formed above the transfer and driver transistors with an insulating film sandwiched therebetween and which are in electrical connection with the transfer and driver transistors. A conventional memory cell having a top gate TFT is explained hereinbelow with reference to FIGS. 1, 2A, 2B, 3 and 4A to 4D.
FIG. 1 is a circuit diagram of SRAM cell. The illustrated SRAM cell is comprised of a flip flop circuit and two transfer transistors Qt1 and Qt2. The flip flop circuit includes two driver transistors Qd1 and Qd2, and two thin film load transistors Q11 and Q12. In a cell array, a complementary bit line DL1 and a word line WL1 are electrically connected to a source/drain terminal and a gate electrode of the transfer transistor Qt1, respectively, and similarly, a complementary bit line DL2 and a word line WL2 are electrically connected to a source/drain terminal and a gate electrode of the transfer transistor Qt2.
The driver transistors Qd1 and Qd2 have source terminals electrically connected to a grounding wire Vss, and drain terminals connected to both source/drain terminals of the transfer transistors Qt1 and Qt2 and drain terminals of the load transistors Q11 and Q12 through nodes N1 and N2, respectively. The load transistors Q11 and Q12 have source terminals electrically connected to a power source wire Vcc. The driver transistor Qd1 and the load transistor Q11 both have gate terminals electrically connected to the node N2, and the driver transistor Qd2 and the load transistor Q12 both have gate terminals electrically connected to the node N1. The driver transistors Qd1 and Qd2 and the load transistors Q11 and Q12 connected in such a manner as above mentioned cooperate with each other to constitute a flip flop circuit.
In the illustrated SRAM cell, the driver transistors Qd1 and Qd2 and the transfer transistors Qt1 and Qt2 are all n-channel MOSFETs, and the load transistors Q11 and Q12 are p-channel MOSFETs. Data are stored in the illustrated SRAM cell in dependence on two stable states of the flip flop circuit working as a bistable circuit. For example, when the node N1 is at a higher level and the node N2 is at a lower level, data is stored as "1", whereas when the node N1 is at a lower level and the node N2 is at a higher level, data is stored as "0".
FIGS. 2A and 2B illustrate a TFT load SRAM unit cell. FIG. 2A illustrates MOSFET section of the cell, whereas FIG. 2B illustrates TFT section of the cell. Unit cells located adjacent to the illustrated unit cell are in mirror-symmetry relation with the illustrated unit cell about long and short sides thereof. Thus, a contact hole is partially shared by the illustrated unit cell and unit cells located adjacent thereto.
FIG. 3 is a cross-sectional view taken along the line III--III in FIGS. 2A and 2B. As illustrated in FIG. 3, field oxide films 202 are formed on a silicon substrate 201, and a gate oxide film 203 is formed in a device activation region on the silicon substrate 201. On the field oxide film 202 and the gate oxide film 203 is formed a gate electrode G1 of a driver transistor which comprises a three-layered structure including a polysilicon film 204, a tungsten silicide film 205 and a silicon film 206 deposited in this order (FIG. 2A illustrates only the tungsten silicide film 205 for simplification). Similarly on the gate oxide film 203 is formed a gate electrode G2 of a transfer electrode or a word line, comprising a polysilicon film 204a, a tungsten silicide film 205a and a silicon film 206a deposited in this order. Sidewalls of the gate electrodes G1 and G2 are covered with sidewall insulating films 207. The silicon substrate 201 is formed at a surface thereof with N- diffusion layers 208a and 209a and further with N+ diffusion layers 208 and 209 which are located adjacent to and making contact with the N- diffusion layers 208a and 209a. A gate electrode G2 of another transfer transistor is formed on the field oxide film 202. The gate electrode G2 of another transfer transistor acting as another word line is comprised of a polysilicon film 204b, a tungsten silicide film 205b, and a silicon film 206b.
The above mentioned components are covered with a first interlayer insulating film 211 on which in turn is formed a grounding wire 213. The grounding wire 213 is connected to diffusion layers (not illustrated) formed in the silicon substrate 201 through a contact hole 212 (see FIG. 2A).
As illustrated in FIGS. 2B and 3, a second interlayer insulating film 214 is deposited over the first interlayer insulating film 211. TFT is formed on the second interlayer insulating film 214 above the grounding wire 213. TFT working as a load transistor includes a TFT source region 215, a TFT drain region 216, a TFT channel region 217 disposed between the source and drain regions 215 and 216, and lightly impurity-doped regions 216a one of which is located adjacent to the TFT drain region 216 and the other is spaced away by a contact hole 220. On the TFT channel region 217 is formed a TFT gate insulating film 218, on which is formed TFT gate electrodes referenced with numerals 219 and 219a. The TFT gate electrode 219a is in contact at a bottom of the contact hole 220 with the silicon film 206, the tungsten silicide film 205, the polysilicon film 204 and a N+ diffusion layer 210.
As illustrated in FIGS. 2B and 3, TFT having the above mentioned structure is covered with a third interlayer insulating film 221, on which a bit line 224 made of aluminum is formed. Thus, a TFT load SRAM cell is completed. The bit line 224 is in contact with the N+ diffusion layer 208 through a bit line contact plug 223 filling a bit line contact hole 222 therewith. The plug 223 is made of tungsten.
FIGS. 4A to 4D illustrate cross-sectional views of the above mentioned SRAM cell, showing fabrication steps of a method of fabricating the same. First, as illustrated in FIG. 4A, the field oxide films 202 are formed on the p-type silicon substrate 201, and the gate oxide film 203 is formed in a device activation region, namely in a region defined between the field oxide films 202. Then, the gate electrode G1 of a driver transistor is formed in the device activation region on the gate oxide film 203. The gate electrode G1 is formed by depositing the polysilicon film 204, the tungsten silicide film 205 and the silicon film 206 on the gate oxide film 203 in this order, and further patterning them by means of photolithography and etching. Similarly, the gate electrodes G2 of the transfer transistors, which act as word lines, are formed on the gate oxide film 203. The gate electrodes G2 are comprised of polysilicon films 204a and 204b, tungsten silicide films 205a and 205b, and silicon films 206a and 206b. The gate electrodes G2 are formed in the same manner as that of the gate electrode G1.
Then, ion implantation is carried out to the silicon substrate 201 by using the gate electrode G2 as a mask to thereby form lightly impurity-doped diffusion layers or N- diffusion layers 208a and 209a in the silicon substrate 201. Then, the sidewall insulating films 207 made of silicon dioxide are formed on sidewalls of the gate electrodes G1 and G2. Then, ion implantation is carried out to the silicon substrate 201 with the gate electrodes G1 and G2 and the sidewall insulating films 207 being used as a mask to thereby form the heavily impurity-doped diffusion layers or N+ layers 208 and 209 located adjacent to the N- diffusion layers 208a and 209a formed just below the sidewall insulating films 207.
Then, as illustrated in FIG. 4B, a resultant is covered with the first interlayer insulating film 211 made of silicon dioxide by means of chemical vapor deposition (CVD). Then, there is formed the grounding wire 213 on the first interlayer insulating film 211. Then, the grounding wire 213 and the first interlayer insulating film 211 are covered with the second interlayer insulating film 214, on which in turn is formed a silicon film 225 from which TFT will be made.
Then, as illustrated in FIG. 4C, a TFT gate insulating film 218 having a thickness of about 20 nm is formed over the silicon film 225. Then, a patterned resist mask 226 is formed over a resultant, and thereafter there is formed the contact hole 220 with the resist mask 226 being used as an etching mask. The silicon film 206, the N+ diffusion layer 209 and the N- diffusion layers 209a appear in the contact hole 220.
Then, as illustrated in FIG. 4D, there are formed the TFT gate electrodes 219 and 219a. The TFT gate electrode 219a is in contact at a bottom of the contact hole 220 with the silicon film 206, the tungsten silicide film 205, the polysilicon film 204 and the N+ diffusion layer 210.
Then, boron ion is implanted into the TFT silicon film 225 with the TFT gate electrodes 219 and 219a being used as a mask to thereby form the TFT source regions 215 and 215a and the TFT drain region 216. However, it should be noted that boron ions are not implanted into portions 216a of the TFT silicon film 225 located just beneath the TFT gate electrode 219a, because the TFT gate electrode 219a acts as a mask to thereby not allow boron ions to be introduced into the portions 216a.
Then, as illustrated in FIG. 3, TFT is entirely covered with the third interlayer insulating film 221, on which the bit line 224 made of aluminum is formed. Thus, a TFT load SRAM cell is completed. The bit line 224 is in contact with the N+ diffusion layer 208 through the bit line contact plug 223 filling the bit line contact hole 222 therewith. The bit line contact plug 223 is made of tungsten.
The above mentioned TFT load SRAM cell and the method of fabricating the same have problems as follows. The first problem is a reduction in current capability or ON-state current of TFT, which in turn causes stability of SRAM cell to lower. In particular, a voltage at a higher level node of a cell is not sufficiently high immediately after data has been written thereinto, data in a cell is not in stable condition. When a current flow into the higher level node from the power source Vcc through TFT, the higher level node is charged and thus transfers into stable condition. However, if current capability or ON-state current of TFT is low, it takes much time for data stored in a cell to become stable. Thus, it is often quite difficult to exactly read out the stored data immediately after data has been written into SRAM cell, and data destruction or soft error would readily take place due to external noises, in particular, radiation.
The reason why the current capability of TFT is reduced is that the silicon film 225 is formed with a high resistance region in the TFT drain region 216 in the vicinity of a contact hole connecting TFT to MOSFET, which region contains no impurities therein or contains impurities only at a low concentration. The region corresponds to the lightly impurity-doped regions 216a illustrated in FIG. 2B and FIG. 3.
The above mentioned high resistance region may be reduced with respect to a resistance by carrying out annealing to thereby thermally diffuse impurities therein after impurities are implanted into the TFT source/drain regions. However, with a semiconductor memory device being more highly integrated and a semiconductor element becoming finer in size, annealing is required to carry out at a lower temperature to thereby depress thermal diffusion of impurities, in order to prevent a channel of MOSFET from becoming shorter. Thus, it is considered that the above mentioned problem about the high resistance region in a top gate TFT will become remarkable.
There has been suggested a SRAM memory cell with polysilicon LDD-PMOS TFT loads by K. Tsutsumi et al., "A high-performance SRAM memory cell with LDD-TFT loads", pp. 23-24.
There has been also suggested a 0.25 .mu.m CMOS process for fast static RAMs featuring 0.25 .mu.m polycide gate surface channel NMOS and PMOS transistors with drive currents of 630 and 300 .mu.A/.mu.m respectively at an off-leakage of 10 pA/.mu.m, by T. F. McNelly et al., "High Performance 0.25 .mu.m SRAM Technology with Tungsten Interpoly Plug", IEEE, 1995, pp. 36.7.1-36.7.4.